Half-bit memory cell array with nondestructive readout

ABSTRACT

A half-bit memory array featuring nondestructive reading uses two X address circuits addressed at different times and coupled by an inverter to read the memory element in a first portion of the operational cycle, and refresh it in a second portion of the operational cycle, without disturbing the gate electrode potential of the memory element at any time during the cycle, and without the refresh signal level being dependent upon the read signal level. Writing is accomplished by disabling the inverter to prevent transfer of the read information to the refresh circuit and substituting in its place a low-impedance data input signal. Fast switching is accomplished by reducing charge transfer operations to a minimum, and the circuit is entirely ratioless to improve speed of operation and circuit size.

United States Patent Morris [451 Jan. 18, 1972 [54] HALF-BIT MEMORY CELLARRAY Primary Examiner-Bemard Konick WITH NQNDESTRUCTIVE RE ABOUTAssistant Examiner-Stuart Hecker Attorney-J. H. McCarthy and Theodore E.Bieber [72] Inventor: Dennis E. Morris, Sunnyvale, Calif.

73 Assignee: Shell Oil Company, New York, NY. [57] ABSTRACT [22] Filed:No 14, 1969 A half-bit memory array featuring nondestructive readinguses two X address circuits addressed at different times and cou- [21]Appl. No.: 876,622 pled by an inverter to read the memory element in afirst portion of the operational cycle, and refresh it in a secondportion 52] U S cl 340/173 FF 340/173 CA of the operational cycle,without disturbing the gate electrode [51] G1 lc 11/34 G1 1c 11/40potential of the memory element at any time during the cycle, [58] Fieid34:0/173 R CA 173 FF and without the refresh signal level beingdependent upon the read signal level. Writing is accomplished bydisabling the in- 56] References Cited verter to prevent transfer of theread information to the refresh circuit and substituting in its place alow-impedance UNITED STATES PATENTS data input signal. Fast switching isaccomplished by reducing charge transfer operations to a minimum, andthe circuit is en- 3,387,286 6/1968 Dennard ..340/l73 R 1 ratioless toimprove Speed of operation and circuit size 3,528,065 9/1970 Christensen..340/l73 R 11 Claims, 2 Drawing Figures 1 ij R EXTERNAL CIRCUITRY I H}'0 (OPTIONAL) To OTHER I f: I 26 ol m2 ROWS +IOV I I o I i O IDATA I 56OUT /I I i I 22 I l l 2e J Ta "32 54 READ L 55 I ES e0 e2 64 (ISIS-"5:4

m 40 42- I- I 38 T 6 WRITE 4 8 I66 52 ii 3 I +|OV +|ov Y l ADDRESS '1I-cEu I T INPUT X ADDRESS 0 I I v To OTHER 1 COLUMNS OUTPUT x ADDRESS II6 CIRCUITRY COMMON TO ROW PATENIEB JAN 1 a me SHEEI 1 OF 2 llllllllJjmu mar

mmwmoo x PDmhDO $6 E 20228 E586 lllll T 2 Q0 No 00 H QE mutt-O o.

me e

L9 N l b E I INVENTOR. DENNIS E. MORRIS Mg m W ATTORNEYS PATENTED JAN 18 1972 SHEET 2 [IF 2 (D I (PRECHARGE) en 2 (INTERNAL DATA TRANSFER) Q 3(OUTPUT WRITE READ INPUT X ADDRESS OUTPUT X ADDRESS Y ADDRESS INVENTOR.DENNIS E. MORRIS HALF-BIT MEMORY CELL ARRAY WITH NONDESTRUCTIVE READOUTBACKGROUND OF THE INVENTION MOSFET (metal oxide silicon field-effecttransistor) memory devices of the prior art depend, in general, upon thetransfer of incremental charges stored on the gate capacitance of one ofthe MOSFET circuit elements, on a line capacitance, or on a capacitiveelement formed on the chip. The limited capacitance of these storageelements severely limits the signal levels obtainable, and thus limitsthe operational speed of the device.

In other instances, the operation of the device depends upon theon-resistance ratio of several MOSFET elements. In the latter case, theratioing of the MOSFET elements imposes undesirable design limitationsand presents fabrication problems.

SUMMARY OF THE INVENTION The present invention overcomes thedisadvantages of the aforementioned prior art devices by providing acompletely ratioless, fast-acting circuit in which all informationtransfer within the internal read-refresh loop is independent of anycapacitive-charge-transfer time constant limitations. The circuit ofthis invention is a half-bit memory cell array, the name being derivedfrom the fact that the cell is composed of only one inverter and sharesthe other inverter which makes up a normal storage flip-flop. Theindividual memory cells have an internal addressing capabilityresponsive to only one of the two coordinates of the bit address (inthis case, the X address). The other coordinate of the bit address (inthis case, the Y address) is applied to circuitry common to a row ofcells.

The circuit of this invention is distinguished, among other things, bythe provision of two separate X-address inputs for each memory cell. Thetwo X-address inputs are operative during different portions of theoperational cycle and provide for the time separation of the readoperation from the refresh operation.

To further improve the reliability of the device, the read operation isnondestructive. However, in order to allow periodic refreshing of thearray, provision is made to automatically refresh and addressed memorycell immediately following its reading.

It is therefore the primary object of the invention to provide afast-acting, ratioless random-access memory array circuit in which allswitching operations are powered by a low-impedance bias source.

It is a further object of the invention to provide inverter meansbetween the data-out bit line and the data-in bit line to render thedata-in signal to the cell independent of the level of the data-outsignal from the cell.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of thedevice of this invention; and

FIG. 2 is a time-amplitude graph showing the time relation of the clockpulses used with the device of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1 in the lightof the pulse diagram of FIG. 2, the output circuit of a MOSFET chipconstructed in accordance with this invention consists of a loadresistor 10, connected in series with an output gate 12 between DC biassources 14 and 16 of differing potential. If the bias source 14 isrelatively positive, and the bias source 16 relatively negative, thepotential at junction 18 will be logic 1 when output gate 12 is enabled,and logic when output gate 12 is blocked.

The logic state of junction 18 can be read at the data-out terminal 20at an appropriate time in the operational cycle by energizing the readgate 22.

To permit extra-fast switching of the output gate 12, a low prebias isapplied to the gate electrode of output gate [2 through prebias gate 24from a prebias source 26. The prebias source 26 is of such potential asto keep the gate electrode of output gate 12 just barely abovethreshold. It will be noted that the output gate 12 is thus normallymaintained in a logic 1 state, and that it is switched to the logic 0state only when a 0" readout occurs (and also during the writeoperation, as explained hereinbelow). Due to the near-threshold prebiasof the gate electrode of output gate 12, the switching from the logic 1"state in response to the 0 readout is essentially instantaneous.

In operation, the cycle starts with the appearance of the 01 pulse. Theappearance of the 01 pulse enables precharge gate 28 and charges thegate electrode of prebias gate 24 as well as capacitor 30 to thenegative 01 clock potential. (Capacitor 30 is a bootstrapping elementand serves to drive prebias gate 24 on harder when the subsequentappearance of the 02 pulse brings the voltage on its right side to logicl). At the same time, the 01 pulse enables isolating gate 32 and thusprecharges the gate electrode of inverter input 34 to negative clockpotential. Inasmuch as 02 is at ground at this moment, the enabling ofinverter input 34 grounds the data in bit line 36 if it is not alreadygrounded.

The appearance of the 61 pulse also charges capacitor 38 to negativeclock potential (Y address being at ground at this time) so as to holdthe data-out bit line 40 at negative clock potential. At the same time,the 01 clock pulse enables bufier precharge gate 42 and thus brings thebuffer line 44 to +10 v., which causes buffer gate 46 to be blocked.Thus, during the 01 pulse, the outputjunction 18 is maintained at logicl The logic condition of each individual memory cell 48 is expressed bythe enabled or blocked condition (representing logic 1" and logic 0,respectively) of the memory gate 50.

When the 01 pulse terminates, isolating gate 32 becomes blocked, and thedata-out bit line 40 remains at negative clock potential due to thecharge on its own bit line capacitance C and on the auxiliary capacitor38. When the 62 pulse now appears, the X-address gate 52 of theaddressed cell 48 is enabled. If the cell 48 was in the logic 1condition, the data-out bit line 40 becomes connected to the +10 v.supply through memory gate 50 and X-address gate 52. On the other hand,if the cell was in the logic 0 condition, memory gate 50 is blocked andthe data-out bit line 40 remains at negative clock potential.

The appearance of the 02 pulse also enables the precharger 54 of theinverter 56 and causes the data-in bit line 36 to go to negative clockpotential. After the cessation of the 02 pulse, the state of the data-inbit line 36 is dictated by the condition of the data-out bit line 40.Inasmuch as the data-out bit line 40 is directly connected to the gateof inverter input 34, inverter input 34 is blocked if the memory cell 48was at logic 1 and is enabled if the memory cell 48 was at logic 0."

Consequently, if the memory cell was at logic 1, the nowgrounded 62clock is isolated from the data-in bit line 40, and the data-in bit line36 remains at negative clock potential due to the action of its owninherent bit line capacitance C On the other hand, if the memory cellwas at logic 0, inverter input 34 is enabled, and the data-in bit lineis driven back to ground by the now-grounded 02 clock.

Upon the appearance of the 03 pulse, X-address gate 58 in the memorycell 48 is enabled, and the logic state of the datain bit line 36 istransferred to the gate electrode of memory gate 50. It will be seenthat the 63 pulse thus serves as a refresh pulse, inasmuch as theenabling of X-address gate 58 will of necessity refresh the previouslyexisting logic state of the gate electrode of memory gate 50.

The appearance of the 03 pulse, by energizing the Y address, alsoenables data input gate 60. If a write operation is to be performedinstead of the restoring operation, a write pulse is applied to thewrite gate 62. This connects the external data source 64 to the data-inbit line 36, and the data to be written is substituted for the restoringdata supplied by the inverter.

enables the buffer gate 46 if the memory cell was at logic O,"

or maintains the buffer gate 46 blocked if the memory cell was at logicI. In the former case, output gate 12 becomes blocked by the applicationof the +10 v. supply to its gate electrode through the buffer gate 46;in the latter case, the gate electrode of output gate 12 retains itsprevious energization.

in either case, the 03 pulse, by enabling prebias disabling gate 70,applies a +10 v. bias to prebias gate 24 to cut off the prebias supplyto output gate 12 during the 03 pulse.

It will be noted that when buffer gate 46 is to be enabled by a logicmemory state, the upper end of capacitor 38 is charged to 01 potential,say l0 v., with respect to the Y address supply just prior to the 03pulse. Conversely, for a logic l memory state, the upper end ofcapacitor 38 is at v. with respect to the Y address supply just beforethe 03 pulse.

When the 03 pulse occurs on a memory 0" cycle, a voltage division occursbetween the then-appearing -10 v. level of the Y address supply andground across the series connection of capacitor 38 and bit linecapacitance C The relatively large capacitance of capacitor 38 aids themaintenance of the logic l level in line 40, thus assuring fastswitching of buffer gate 46 even though this switching operation relieson a charge transfer between data-out bit line 40 and the gate electrodeof buffer gate 46, rather than on a connection of buffer gate 46 to alow-impedance power supply.

If the 03 pulse occurs on a memory l cycle, the upper end of capacitor38 merely drops from +10 v. to ground potential when Y address goesnegative and buffer gate 46 does not switch.

During a write operation, the effect of the logic state of the data-outbit line 40 is overridden by the enabling state of inverter-disablinggate 66 by the write pulse. Consequently, a write operation will alwaysproduce a +10 V. potential in the data-out bit line 40, and buffer gate46 is always blocked during a write operation.

It follows from the above description that the logic state of outputjunction 18 can be read to provide a data output from the chip at anytime between the onset of the 03 pulse and the onset of the following 91pulse. At all other times, the output junction 18 is held at logic l bythe prebias circuit.

lclaim:

1. A ratioless random-access memory array comprising:

a. a plurality of memory cells each including a memory elementswitchable between a conductive and a nonconductive state; a source ofDC potential representing a first logic state; first bit line means;precharge means operative during a first portion of the operationalcycle of said memory array for precharging said first bit line means toa precharge potential representing a second logic state; first thicknessmeans in each of said cells responsive to a selected first addresscoordinate of the addressed cell and operative during a second portionof said operational cycle to connect said first bit line means to saidDC potential source through said memory element so as to change thelogic state of said first bit line if the said memory element isconductive;

second bit line means;

. second address means in each of said cells responsive to said firstaddress coordinate but operative during a third portion of saidoperational cycle to connect said memory element to said second bit linemeans so as to switch said memory element to the conductivity statedetermined by app- the logic state of said second bit line means; and h.inverter means interposed between said first and second bit line meansto produce, during said third portion of said operational cycle, a logicstate which is the inverse of the logic state existing in said first bitline means during said second portion of said operational cycle.

2. The array of claim 1, in which each of said cells has a secondaddress coordinate, and which there is a plurality of first and secondbit line means, any given first and second bit line means being commonto all cells whose second address coordinate is the same; and secondaddress means responsive to a selected second address coordinate forconnecting a selected one of said bit line means to data output circuitmeans.

3. The array of claim 1, further comprising a source of write pulses, asource of input data, and means responsive to the appearance of writepulse to disable said inverter means and to connect said second bit linemeans to said input data source.

4. A random-access memory array, comprising:

a. a plurality of individually addressable memory cells;

b. first bit line means;

c. means for establishing in said first bit line means a logic stateopposite to the logic state of an addressed memory element;

d. second bit line means;

e. inverter means connected between said first and second bit line meansto establish in said second bit line means a logic state equal to thelogic state of said addressed memory element; and

f. means for establishing in said memory element the logic state of saidsecond bit line means.

5. The array of claim 4, in which the establishment of said oppositelogic state in said first bit line means does not affect the logic stateof said memory element.

6. The array of claim 4, in which all of said logic state establishingmeans are ratioless.

7. The array of claim 4, further comprising writing means arranged toselectively disable said inverter means and establish in said second bitline means the logic state of externally supplied input data.

8. A random-access memory array, comprising:

a. a plurality of individually addressable memory cells;

b. bit line means;

c. means for establishing in said bit line means a logic stateindicative of the logic state of an addressed memory cell;

d. output circuit means including output gate means;

e. prebias means arranged to maintain said output gate means in a firstlogic state but at a potential just sufficient to prevent its switchingto the opposite logic state;

f. means for disabling said prebias means during a predetermined portionof the operational cycle of said array; and

g. buffer means responsive to the logic state in said but line forbiasing said output gate means into said opposite logic state duringsaid predetermined portion of said operational cycle upon the presenceof a predetermined logic state in said bit line.

9. The array of claim 8, in which said predetermined bit line logicstate is the same as said first logic state of said output gate means.

10. The array of claim 8, further comprising precharge means forprecharging said buffer means into a predetermined logic state during afirst portion of the operation cycle of said array, and address gatemeans for rendering said buffer means responsive to said bit line logicstate during a second portion of said operational cycle.

11. The array of claim 10, further comprising capacitive means connectedbetween said but line means and said address gating means so as toincrease, during said second portion of said operational cycle, the bitline logic potential available to change the logic state of said buffermeans.

1. A ratioless random-access memory array comprising: a. a plurality ofmemory cells each including a memory element switchable between aconductive and a nonconductive state; b. a source of DC potentialrepresenting a first logic state; c. first bit line means; d. prechargemeans operative during a first portion of the operational cycle of saidmemory array for precharging said first bit line means to a prechargepotential representing a second logic state; e. first thickness means ineach of said cells responsive to a selected first address coordinate ofthe addressed cell and operative during a second portion of saidoperational cycle to connect said first bit line means to said DCpotential source through said memory element so as to change the logicstate of said first bit line if the said memory element is conductive;f. second bit line means; g. second address means in each of said cellsresponsive to said first address coordinate but operative during a thirdportion of said operational cycle to connect said memory element to saidsecond bit line means so as to switch said memory element to theconductivity state determined by the logic state of said second bit linemeans; and h. inverter means interposed between said first and secondbit line means to produce, during said third portion of said operationalcycle, a logic state which is the inverse of the logic state existing insaid first bit line means during said second portion of said operationalcycle.
 2. The array of claim 1, in which each of said cells has a secondaddress coordinate, and which there is a plurality of first and secondbit line means, any given first and second bit line means being commonto all cells whose second address coordinate is the same; and secondaddress means responsive to a selected second address coordinate forconnecting a selected one of said bit line means to data output circuitmeans.
 3. The array of claim 1, further comprising a source of writepulses, a source of input data, and means responsive to the appearanceof write pulse to disable said inverter means and to connect said secondbit line means to said input data source.
 4. A random-access memoryarray, comprising: a. a plurality of individually addressable memorycells; b. first bit line means; c. means for establishing in said firstbit line means a logic state opposite to the logic state of an addressedmemory element; d. second bit line means; e. inverter means connectedbetween said first and second bit line means to establish in said secondbit line means a logic state equal to the logic state of said addressedmemory element; and f. means for establishing in said memory element thelogic state of said second bit line means.
 5. The array of claim 4, inwhich the establishment of said opposite logic state in said first bitline means does not affect the logic state of said memory element. 6.The array of claim 4, in which all of said logic state establishingmeans are ratioless.
 7. The array of claim 4, further comprising writingmeans arranged to selectively disable said inverter means and establishin said second bit line means the logic state of externally suppliedinput data.
 8. A random-access memory array, comprising: a. a pluralityof individually addressable memory cells; b. bit line means; c. meansfor establishing in said bit line means a logic state indicativE of thelogic state of an addressed memory cell; d. output circuit meansincluding output gate means; e. prebias means arranged to maintain saidoutput gate means in a first logic state but at a potential justsufficient to prevent its switching to the opposite logic state; f.means for disabling said prebias means during a predetermined portion ofthe operational cycle of said array; and g. buffer means responsive tothe logic state in said but line for biasing said output gate means intosaid opposite logic state during said predetermined portion of saidoperational cycle upon the presence of a predetermined logic state insaid bit line.
 9. The array of claim 8, in which said predetermined bitline logic state is the same as said first logic state of said outputgate means.
 10. The array of claim 8, further comprising precharge meansfor precharging said buffer means into a predetermined logic stateduring a first portion of the operation cycle of said array, and addressgate means for rendering said buffer means responsive to said bit linelogic state during a second portion of said operational cycle.
 11. Thearray of claim 10, further comprising capacitive means connected betweensaid but line means and said address gating means so as to increase,during said second portion of said operational cycle, the bit line logicpotential available to change the logic state of said buffer means.